The present invention relates to polishing methods and systems for polishing a workpiece, such as a semiconductor wafer. The present invention also relates to Chemical Mechanical Polishing (CMP) methods and systems thereof. The present invention additionally relates to robot-assisted methods and systems for polishing semiconductor wafers. Additionally, the present invention relates to methods and systems for monitoring tension in robot-assisted CMP machines.
Machines for polishing and machines for cleaning wafers and disks in the electronics industry are generally well known. For example, semiconductor wafers, magnetic disks, and other workpieces often come in the form of flat, substantially planar, circular disks. In the manufacture of integrated circuits, semiconductor wafer disks are sliced from a silicon ingot and prepared for further processing. After each wafer is sliced from the ingot, it must be thoroughly polished and then cleaned, rinsed, and dried to remove debris from the surface of the wafer. Thereafter, a series of steps are performed on the wafer to build the integrated circuits on the wafer surface, including applying a layer of microelectronic structures and thereafter applying a dielectric layer. Typically, after the layers are fabricated on the wafer surfaces, the wafers must be planarized to remove excess material and imperfections.
After each processing step, it is often desirable to thoroughly clean, rinse, and dry the wafers to ensure that debris is removed from the wafers. Thus, a method and apparatus for quickly and efficiently cleaning, rinsing, and drying wafers is needed which facilitates high wafer throughput, while at the same time thoroughly cleaning and drying the wafers with a minimum of wafer breakage.
Integrated circuit devices are typically formed on substrates, most commonly on semiconductor substrates, by the sequential deposition and etching of conductive, semiconductive, and insulative film layers. As the deposition layers are sequentially deposited and etched, the uppermost surface of the substrate, i.e., the exposed surface of the uppermost layer on the substrate, develops a successively more topologically rugged surface. This occurs because the height of the uppermost film layer, i.e., the distance between the top surface of that layer and the surface of the underlying substrate, is greatest in regions of the substrate where the least etching has occurred, and least in regions where the greatest etching has occurred.
This non-planar surface presents a problem for the integrated circuit manufacturer. The etching step is typically prepared by placing a resist layer on the exposed surface of the substrate, and then selectively removing portions of the resist to provide the etch pattern on the layer. If the layer is non-planar, photolithographic techniques of patterning the resist layer might not be suitable because the surface of the substrate may be sufficiently non-planar to prevent focusing of the lithography apparatus on the entire layer surface.
Chemical mechanical polishing or planarizing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted in a wafer head, with the surface of the substrate to be polished exposed. The substrate supported by the head is then placed against a rotating polishing pad. The head holding the substrate may also rotate, to provide additional motion between the substrate and the polishing pad surface. Further, a polishing slurry is supplied to the pad to provide an abrasive chemical solution at the interface between the pad and the substrate. A polishing slurry typically includes an abrasive and at least one chemically reactive agent therein, which are selected to enhance the polishing of the topmost film layer of the substrate. For polishing of an oxide layer, the slurry can be composed of silica grit. The grit is formed by fuming and is then placed in a basic pH solution. The solution is then strongly sheared by blending so that the grit remains in colloidal suspension for long periods. For metal polishing, the grit may be formed from either silica or alumina.
The combination of polishing pad characteristics, the specific slurry mixture, and other polishing parameters can provide specific polishing characteristics. Thus, for any material being polished, the pad and slurry combination is theoretically capable of providing a specified finish and flatness on the polished surface. It must be understood that additional polishing parameters, including the relative speed between the substrate and the pad and the force pressing the substrate against the pad, affect the polishing rate, finish, and flatness. Therefore, for a given material whose desired finish is known, an optimal pad and slurry combination may be selected. Typically, the actual polishing pad and slurry combination selected for a given material is based on a trade off between the polishing rate, which determines in large part the throughput of wafers through the apparatus, and the need to provide a particular desired finish and flatness on the surface of the substrate.
Because the flatness and surface finish of the polished layer is dictated by other processing conditions in subsequent fabrication steps, throughput insofar as it involves polishing rate must often be sacrificed in this trade off. Nonetheless, high throughput is essential in the commercial market since the cost of the polishing equipment must be amortized over the number of wafers being produced. Of course, high throughput must be balanced against the cost and complexity of the machinery being used. Similarly, floor space and operator time required for the operation and maintenance of the polishing equipment incur costs that must be included in the sale price.
An additional limitation on polishing throughput arises because the pad""s surface characteristics change as a function of the polishing usage, and it also becomes compressed in the regions where the substrate was pressed against it for polishing. This condition, commonly referred to as xe2x80x9cglazingxe2x80x9d, causes the polishing surface of the polishing pad to become less abrasive to thereby decrease the polishing rate over time. Glazing thus tends to increase the polishing time necessary to polish any individual substrate. Therefore, the polishing pad surface must be periodically restored, or conditioned, in order to maintain desired polishing conditions and achieve a high throughput of substrates through the polishing apparatus. Pad conditioning typically involves abrading the polishing surface of the pad to both remove any irregularities and to roughen the surface.
Pad conditioning, although it raises the average polishing rates, introduces its own difficulties. If it is manually performed, its consistency is poor and it incurs operator costs and significant downtime of the machinery, both decreasing the cost adjusted throughput. If the pad conditioning is performed by automated machinery, care must be taken to assure that the surface abrading does not also gouge and damage the polishing pad. Furthermore, if the relative motion between the conditioning tool and pad is primarily provided by the pad rotation, the relative velocity and dwell time varies over the radius of the pad, thus introducing a radial non-uniformity into the reconditioned pad. Such problems can be further exacerbated if the CMP system in use is subject to inherent shifting and uncontrollable mechanisms.
An example of a CMP system that is currently utilized in major semiconductor fabrication facilities throughout the world is the Mirra planarizing machine manufactured by Applied Materials Corporation of Santa Clara, Calif. Such a machine typically includes a robot X-belt, which often shifts position, resulting in a broken belt before the end of its lifetime, which is supposed to be in a range of 6 months and beyond. Thus, the lifetime of such a robot X-belt (i.e., a belt) cannot be controlled accurately in such CMP systems and machines. This often results in wafer damage stemming form robot blades during placement or remove of the wafer from an associated cassette, which can be utilized to store a substrate.
Based on the foregoing, the present inventor has concluded that a need exists for an improved method and system for monitoring tension in such belts utilized in CMP machines and processes. By successfully monitoring the tension of such belts, the lifetime of the belt can be controlled accurately. Additionally, a successful tension monitoring method and system would prevent breakage in such belts and damage to the wafers before, during and after wafer transfer.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved polishing method and system for polishing a workpiece, such as a semiconductor wafer.
It is another aspect of the present invention to provide an improved Chemical Mechanical Polishing (CMP) method and system;
It is still another aspect of the present invention to provide an improved method and system for polishing semiconductor wafers.
It is also an aspect of the present invention to provide improved methods and systems for monitoring tension in robot-assisted CMP machines.
It is one other aspect of the present invention to provide an online tension monitor method and system for robot-controlled belts utilized in CMP devices.
The above and other aspects of the present invention can thus be achieved as is now described. A method and system for monitoring tension associated with a robot-controlled belt utilized in a semiconductor wafer polishing apparatus are disclosed herein. A belt tension monitor can be adapted for use with the semiconductor wafer polishing apparatus to detect a variable tension of the robot-controlled belt. An upper tension limit and a lower tension limit of the robot-controlled belt may then be monitored utilizing the belt tension monitor to prevent a breakage of the robot-controlled belt during a semiconductor wafer polishing operation thereby extending a life of the robot-controlled belt.
The belt tension monitor can be installed at an inertial pulley of a robot associated with the semiconductor wafer polishing apparatus to detect the variable tension of the robot-controlled belt. A belt tension signal can be detected utilizing the belt tension monitor. The belt tension signal can be transferred to a load cell associated with the semiconductor wafer polishing apparatus. The belt tension signal may then be further transferred from the load cell to an indicator and thereafter displayed for a user. Additionally, the upper tension limit and the lower tension limit of the robot-controlled belt can be automatically determined utilizing the belt tension monitor. The life the robot-controlled belt can also be predicted utilizing data collected from the belt tension monitor.
The belt tension monitor itself can include a load cell fixed truss, a pulley support truss a load cell, and an indicator. A tension force of the robot-controlled belt thus acts upon a pulley and is thereafter transferred to the load cell by way of a pulley shaft and the pulley support truss. The belt tension value is displayed by the indicator, which thereafter can automatically send an alarm signal to the semiconductor wafer polishing apparatus, if the tension value is not between the upper tension limit and the lower tension limit. The semiconductor wafer polishing apparatus can generally be configured as a CMP apparatus.